Chiplet– tag –
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Intel Foundry Leverages U.S. Advanced Packaging (Foveros, EMIB) to Power Next-Gen AI Semiconductors
Intel Newsroom USA Overview Intel Foundry is accelerating the realization of next-generation AI semiconductors through its advanced packaging technologies developed in U.S. facilities. Utilizing Foveros stacking, EMIB silicon bridges, an... -
Qnity Electronics Accelerates AI-Centric Advanced Packaging R&D with Expanded imec Collaboration
Converge Digest Belgium Overview Qnity Electronics has significantly expanded its strategic collaboration with imec, a world leader in nanoelectronics, to bolster long-term R&D in advanced semiconductor packaging crucial for AI and h... -
Intel and Lens Technology Form Strategic Alliance to Accelerate Glass Substrate-Based Advanced Semiconductor Packaging for AI Era
Intel Newsroom USA Overview Intel and Lens Technology announced a strategic collaboration to accelerate the development of glass substrate-based packaging solutions for advanced semiconductors, critical for the AI era. This partnership a... -
ECTC2026 Unveils Future of Semiconductor Packaging: Precision Adhesives and Low-Temperature Hybrid Bonding for HBM Integration
Tech I Japan Overview ECTC2026 highlighted critical R&D in advanced semiconductor packaging, showcasing innovations in chiplet integration, hybrid bonding, and opto-electronic convergence. Key presentations included Mitsui Chemicals ... -
Sheen Technology Details Evolving TIM Requirements for AI Chips, Emphasizing High Thermal Conductivity and Low Thermal Resistance for Liquid Cooling
Sheen Technology Taiwan Overview Sheen Technology has published a comprehensive guide outlining the evolving requirements for Thermal Interface Materials (TIMs) in high-performance AI chips. Driven by advanced packaging such as 2.5D/3D s... -
Amkor to Invest $7 Billion in Arizona for Advanced AI Chip Packaging, Shifts Korean SiP Production to Vietnam
Seeking Alpha USA Overview Amkor Technology is making a monumental $7 billion investment to construct an advanced packaging and test campus in Arizona, slated for production by early 2028, to address the escalating demand for AI chips. T... -
2.5D Packaging and HBM Integration Accelerate for AI Accelerators: TSMC CoWoS and Samsung I-CubeS Drive Towards 5.5x Reticle Sizes by 2026
Econ Market Research Global Overview The adoption of HBM-integrated 2.5D packaging for AI accelerators is rapidly expanding, with TSMC and Samsung spearheading the technological advancements. TSMC's CoWoS platform now supports silicon in... -
Intel’s EMIB Dominates AI Packaging with Google Adoption, Prompting TSMC to Develop Similar Tech Amidst CoWoS Constraints
Benzinga USA Overview Intel's EMIB technology is establishing a significant competitive advantage in advanced chip packaging for AI workloads, exemplified by Google's adoption of EMIB-T in its 9th-generation TPUs. Facing CoWoS capacity f... -
Ayar Labs Accelerates Commercial Deployment of Optical I/O Chiplets to Revolutionize AI/HPC Performance, Breaking Data Center Bottlenecks
Lightwave Online United States Overview Ayar Labs has announced new partnerships to accelerate the commercial deployment of its silicon photonics-based optical I/O chiplets. This technology directly integrates optical interconnects with ... -
DAC 2026 Highlights ‘True Challenges of AI Chip Creation’: Debating Design Complexity and Soaring Costs
EE Times USA Overview At the 2026 Design Automation Conference (DAC), a session on 'The True Challenges of AI Chip Creation' emphasized the extreme complexity and escalating costs of the design and manufacturing processes. AI chips face ...
