Interposer– tag –
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imec Breaks New Ground: III-V Chiplets on RF Silicon Interposer Achieve 100x Capacitance Density Boost and Sub-600nm Precision
OriginBrief ベルギー Overview imec has announced a significant breakthrough in heterogeneous integration, successfully integrating III-V chiplets onto a 300mm RF silicon interposer platform. This achievement delivers a 10-100x increase i... -
TSMC Accelerates CoPoS Packaging Development, Standardizing 310x310mm Panel Format; Introduces Glass Core Substrate for CoWoS Towards Late 2028 Mass Production
TrendForce Taiwan Overview TSMC is accelerating the development of its CoPoS (Chip-on-Panel-on-Substrate) packaging architecture, standardizing a 310x310mm panel format, with pilot production targeted for 2027 and mass production in late... -
imec Unleashes High-Density MIMCAP RF Interposer for D-Band Millimeter-Wave and Sub-THz Communications, Accelerating III-V Chiplet Integration
imec ベルギー Overview imec has unveiled a high-density MIMCAP RF interposer specifically engineered for demanding D-band and sub-THz wireless front-ends, alongside hundreds of gigahertz data center links. This innovative platform priori... -
Glass Substrates: The Next Frontier in AI Packaging and the Race to Mass Production
The Economy South Korea Overview Glass substrates are rapidly emerging as a transformative technology in advanced AI chip packaging, poised to replace conventional organic substrates and silicon interposers by offering superior dimension... -
Lightmatter Unveils 114Tbps Passage M1000 3D Photonic Interposer and 50Tbps Optical I/O Laser at InterConnect 2026, Joins NVIDIA NVLink Fusion Ecosystem
Lightmatter USA Overview At its InterConnect 2026 keynote, Lightmatter revealed a new category of lasers capable of delivering 50 Tbps of optical I/O and the Passage M1000 3D Photonic Interposer, offering 114 Tbps I/O, to enable a photon... -
Samsung and Intel Pioneer Low-Warpage Solutions for Advanced Electronics Packaging, Boosting Reliability
PatSnap Eureka Global Overview Samsung and Intel are spearheading efforts to reduce warpage in electronics packaging components. Samsung leverages its I-Cube technology and optimized package stack designs to match thermal expansion chara... -
TSMC Repurposes Mature Node Capacity to CoWoS for AI Accelerators Amid Critical Supply Shortage
Tom's Hardware Taiwan Overview TSMC is reallocating 40-90nm mature node capacity to expand its CoWoS advanced packaging and silicon interposer fabrication, directly addressing a critical supply bottleneck for AI accelerators. This strate... -
Rapidus Explores Panel-Level Packaging on Glass Substrates for Next-Gen AI/HPC Processors
Tom's Hardware Japan Overview Japanese semiconductor firm Rapidus is actively exploring the adoption of panel-level packaging (PLP) on large 600mm x 600mm glass panels for manufacturing high-end multi-chiplet processors designed for AI a... -
Glass Substrates Emerge as Next-Generation Solution to AI Chip Packaging Bottleneck
TrendForce Taiwan Overview Glass substrates are gaining significant traction as a next-generation material poised to overcome the limitations of traditional organic substrates and resolve critical bottlenecks in AI chip packaging. Offeri... -
POET Technologies’ Optical Interposer Aims to Unlock $146B AI Semiconductor Opportunity by Integrating Photonics at Wafer-Scale
The Motley Fool USA Overview POET Technologies' Optical Interposer is a silicon-based platform designed to integrate photonic components directly with electronic circuits at the wafer level, aiming to reduce latency and power consumption...
