Panel Level Packaging– tag –
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Semiconductor Back-End
ECTC 2026 Highlights Advanced Packaging Future: Glass Substrates and FOPLP at the Core of System Innovation
Advanced Packaging Magazine USA Overview ECTC 2026 emphasized a structural shift in semiconductor innovation, moving beyond transistor scaling to packaging and integration technologies. Noteworthy advancements in heterogeneous integratio... -
Semiconductor Back-End
ASMPT’s Advanced Packaging Business Achieves Record Sales in H1 2026, Driven by Surging AI Demand
ASMPT Singapore Overview ASMPT reported robust financial results for the first half of 2026, with its Advanced Packaging (AP) business achieving record sales, significantly propelled by escalating AI demand. Key contributors included The... -
Semiconductor Back-End
ASE Technology Bets Big on AI: $10.5 Billion Record Capex to Double Advanced Packaging by 2027
TrendForce Taiwan Overview ASE Technology Holding is significantly increasing its 2026 capital expenditure to a record $10.5 billion, aiming to double the revenue of its leading-edge advanced packaging (LEAP) business by 2027. This ambit... -
Semiconductor Back-End
TSMC Moves to Large-Format Glass Substrates with CoPoS to Address CoWoS Capacity for AI Chips, Targeting 2028-2029 Mass Production
36Kr, Semiconductor Industry Watch, AI Weekly Taiwan Overview TSMC has launched a pilot line for its CoPoS (Chip-on-Panel-on-Substrate) advanced packaging at Taiwan's VisEra, aiming to alleviate the critical CoWoS capacity bottleneck for... -
Semiconductor Back-End
Applied Materials Finds New Equipment Opportunities in PLP for AI Accelerators; KLA’s Process Control Gains Criticality for Complex AI Chips
TIKR.com USA Overview Applied Materials is capitalizing on new equipment opportunities within Panel-Level Packaging (PLP) as AI accelerators integrate more processors and memory, shifting from traditional circular wafers to rectangular p... -
Semiconductor Back-End
Powertech and Broadcom Launch $400M Singapore Joint Venture to Expand FOPLP Manufacturing for AI ASICs
Taipei Times Taiwan Overview Powertech Technology has approved a $400 million joint venture with Broadcom in Singapore to establish advanced Panel-Level Packaging (PLP) manufacturing capabilities, focusing on additive fine-line RDL techn... -
Semiconductor Back-End
Powertech Technology and Broadcom Establish $400 Million Singapore FOPLP Joint Venture for AI ASICs Manufacturing
DigiTimes Taiwan Overview Powertech Technology (PTI) has approved a $400 million investment in a joint venture with Broadcom in Singapore to build Fan-Out Panel-Level Packaging (FOPLP) manufacturing capacity. This strategic move aims to ... -
Semiconductor Back-End
Taiwan’s Grand Process Technology Partners with Germany’s Singulus to Enter Panel-Level Packaging (PLP) Market, Offering AI/HPC Solutions
Taiwan News Taiwan Overview Taiwan's Grand Process Technology Corp. announced its entry into the panel-level packaging (PLP) market through a strategic alliance with its subsidiary Challentech International Corp. and Germany's Singulus T... -
Semiconductor Back-End
eWeek Reports on Critical AI Chip Bottlenecks: Advanced Packaging Identified as Key Solution
eWeek USA Overview A new eWeek report highlights that AI chip performance is confronting significant bottlenecks, deeming advanced packaging technologies essential for resolution. Critically, the scarcity of high-density integration tech... -
Semiconductor Back-End
Intel and TSMC Champion Panel-Level Packaging, Projecting a Tenfold Market Expansion
The Elec South Korea Overview Intel and TSMC are aggressively pursuing Panel-Level Packaging (PLP) technology, a move anticipated to expand the associated market tenfold. PLP offers significant production efficiency and cost advantages o...