TSMC– tag –
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Semiconductor Back-End
NVIDIA’s CoWoS Bottleneck Eases, HBM Supply Emerges as Primary Constraint for AI Accelerators
24/7 Wall St. USA Overview TSMC's CoWoS advanced packaging capacity for AI accelerators is expanding, projected to reach 35,000 wafers/month by late 2026 and up to 140,000 wafers/month by 2027, alleviating a long-standing bottleneck. How... -
Semiconductor Back-End
TSMC Repurposes Mature Node Capacity to CoWoS for AI Accelerators Amid Critical Supply Shortage
Tom's Hardware Taiwan Overview TSMC is reallocating 40-90nm mature node capacity to expand its CoWoS advanced packaging and silicon interposer fabrication, directly addressing a critical supply bottleneck for AI accelerators. This strate... -
Market Trends
AI Factory Power Draw Reshapes Grid Calculus: Direct Liquid Cooling Becomes Essential as Demand Soars
Computer Weekly UK Overview The exponential growth of AI factories is pushing data center power consumption to unprecedented levels, posing critical challenges for existing electrical grids. High-density AI processing via GPUs now mandat... -
Market Trends
Agentic AI Drives Supply Chain Transformation: From Chaos to Autonomous Operations by 2026
Orbit Analytics USA Overview By 2026, agentic AI is fundamentally shifting supply chains from reactive chaos to proactive autonomous operations. Unlike traditional chatbots, agentic AI autonomously acts, orchestrates workflows, and execu... -
Market Trends
Custom AI ASIC Landscape in May 2026: Broadcom, Google TPUs, Meta MTIA Face CoWoS Bottleneck
Tom's Hardware USA Overview As of May 2026, major tech players like Google (TPU), Meta (MTIA), and Broadcom (XDSiP platform) are actively developing custom AI ASICs to challenge NVIDIA's dominance and optimize specialized AI workloads. H... -
Semiconductor Back-End
Glass Substrates Emerge as Next-Generation Solution to AI Chip Packaging Bottleneck
TrendForce Taiwan Overview Glass substrates are gaining significant traction as a next-generation material poised to overcome the limitations of traditional organic substrates and resolve critical bottlenecks in AI chip packaging. Offeri... -
Semiconductor Back-End
TSMC Accelerates CoWoS and SoIC Expansion to Quell AI Chip Bottleneck, Targets 4x Capacity by 2026
FinancialContent - Stock Market Taiwan Overview TSMC is aggressively expanding its CoWoS and SoIC advanced packaging capacity to address the soaring demand for AI chips, aiming to increase monthly wafer output from approximately 35,000 u... -
Photonics
Co-Packaged Optics Emerges as Critical AI Data Center Interconnect to Slash Power, Boost Bandwidth by 2026
Fibermart International Overview Co-Packaged Optics (CPO) is poised to revolutionize hyper-scale AI data centers by integrating optical components directly with computing chips, enabling significant improvements in power efficiency, band... -
New Technology
JSR Fortifies Advanced Semiconductor Material Production and R&D in Taiwan to Meet Surging AI Demand
JSR株式会社 Japan Overview JSR, a leading semiconductor materials manufacturer, announced a significant expansion of its production and R&D capabilities in Taiwan, effective April 2026. This strategic move, driven by key customer req... -
Semiconductor Back-End
TSMC Unveils SoIC 3D Stacking Roadmap: Achieving 4.5µm Pitch by 2029, Enabling Face-to-Face Chiplet Integration for Fujitsu Monaka CPU
専門メディア Taiwan Overview TSMC has revealed its SoIC (System on Integrated Chips) 3D stacking roadmap, targeting a 4.5-micron pitch by 2029, down from today's 6 microns. This advanced face-to-face (F2F) chiplet stacking technology, pa...