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Intel EMIB-T vs TSMC CoWoS: AI Packaging Roadmaps to 2029

TechNews Taiwan
Overview
Intel’s EMIB-T is emerging as a viable alternative to TSMC’s CoWoS as supply bottlenecks for AI chip packaging increase. While CoWoS remains the choice for high-bandwidth requirements, EMIB-T offers a scalable silicon bridge architecture that could diversify the supply chain for logic chips and custom ASICs.
In Depth

Key Findings

Market research firm Prismark reports that chip designers are evaluating Intel’s EMIB-T technology to mitigate supply constraints associated with TSMC’s CoWoS. While the two 2.5D packaging technologies may not fully replace one another, they are expected to divide the market based on technical requirements: high-end chips requiring maximum bandwidth will likely stick with CoWoS, while certain logic chips, custom ASICs, and products with lower memory integration needs may shift to EMIB or EMIB-T.

Technical Details

The two technologies differ in their interconnect architectures. CoWoS utilizes an interposer to integrate multiple chips and High Bandwidth Memory (HBM). In contrast, EMIB embeds small silicon bridges within an organic package substrate for high-speed data transfer, avoiding the need for large-area silicon interposers.

Intel’s EMIB-T roadmap shows significant scaling in package size and density:

  • 2023: 80 × 80 mm size, 12 silicon bridges, and a die-to-die pitch of 55/45 μm.
  • 2026: 120 × 120 mm size, 20 silicon bridges, and a pitch of 40 μm.
  • Post-2028: 120 × 240 mm size, 12 to 14 reticle sizes, 40+ silicon bridges, and a pitch of 40/35 μm.
  • Long-term: Over 240 × 240 mm size, over 40 reticle sizes, 200+ silicon bridges, and a pitch of 25 μm.

Background and Context

TSMC is also expanding CoWoS capabilities. By 2026, TSMC will have mass production capability for interposers up to 5.5 reticle sizes with yields exceeding 98%. Plans for 2028 include expanding to 14 reticle sizes to support 20 HBM units, increasing further in 2029 to over 14 reticle sizes and 24 HBM units. This coincides with the adoption of CoWoS-L for Nvidia’s Blackwell and Rubin chips.

Significance and Outlook

The industry faces a critical bottleneck in advanced substrates. Prismark predicts that the area demand for advanced AI/HPC and large-size FCBGA substrates will grow at a CAGR exceeding 45% from 2025 to 2030, with demand expected to exceed supply starting in 2027. Although over 10 ABF substrate suppliers have committed to capacity expansions, supply remains tight, making the availability of alternative packaging routes like EMIB-T strategically important.

Source: https://technews.tw/2026/11/02/cowos-supply-bottlenecks-intel-emib-t-alternative-packaging/

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