Key Findings
TSMC is reportedly planning to double its Chip-on-Wafer-on-Substrate (CoWoS) production capacity by 2028, aiming to reach 260,000 300mm wafer equivalents per month. This expansion from approximately 130,000 wafers per month at the end of 2026 is a direct response to the escalating demand for AI and high-performance computing (HPC) chips, which are heavily reliant on advanced packaging solutions.
Technical Details
- CoWoS is a 2.5D packaging technology that integrates logic dies, such as GPUs and custom accelerators, with High Bandwidth Memory (HBM) on a silicon interposer or RDL (Redistribution Layer) structure. This integration provides superior bandwidth, lower latency, and improved energy efficiency compared to traditional packaging methods.
- TSMC is continuously advancing its CoWoS solutions, with plans to certify solutions supporting interposers up to 5.5 times the maximum mask area in 2025, with mass production scheduled for 2026. This signifies the capability to integrate increasingly complex and larger AI chips.
Background and Context
The explosive growth of the AI chip market has created unprecedented demand for advanced packaging technologies. CoWoS plays a critical role by enabling the integration of multiple chiplets and HBM stacks within a single package, delivering performance and power efficiency unattainable with conventional methods. TSMC’s CoWoS technology has become a cornerstone for leading AI chip developers like Nvidia and AMD, solidifying its dominant position in the advanced packaging landscape.
Strategic Significance and Outlook
While TSMC’s capacity doubling plan underscores its central role in the AI semiconductor supply chain, the overall market demand is so immense that even this significant increase will not fully saturate the market. Competitors, including Samsung and SK hynix, are expected to continue winning substantial orders for HBM and related packaging services, highlighting a broader industry-wide effort to scale advanced packaging capabilities. This competitive dynamic will likely drive further innovation and accelerate the development of future AI hardware architectures.
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