Semiconductor Back-End– category –
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TSMC to Boost CoWoS Capacity Tenfold to 130K Wafers/Month by Late 2026, Accelerates Glass-Substrate CoPoS for AI Chips
Tom's Hardware USA Overview TSMC is aggressively expanding its advanced packaging capacity, projecting a tenfold increase in CoWoS production to over 130,000 wafers per month by the end of 2026 to meet surging AI demand. Despite this, de... -
Semiconductor Back-End Weekly Report May 7, 2026
📄 Weekly Report June 07, 2026 (PDF) — Download Weekly Report June 07, 2026 (PDF) — DownloadDownload 🎙 Podcast June 07, 2026 (MP3) — Play & Download Semiconductor_BackEndEnglishPodcast_20260607.mp3Download View Past Weekly Reports→ -
IEEE ECTC 2026 Program Reveals Latest Research in Advanced Packaging, Including 3D Integration, Hybrid Bonding, and New Substrate Materials
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The program for the 76th IEEE Electronic Components and Technology Conference (ECTC) unveiled a wide array of cutting-edge research in advanced packaging, focusing ... -
Tsinghua University Develops 3D Chip Design Tool Tailored for Huawei’s ‘LogicFolding’ Architecture
Tom's Hardware China Overview Tsinghua University in China has developed a 3D chip design tool specifically tailored for Huawei’s 'LogicFolding' architecture. This tool aims to optimize chip performance and efficiency for AI and HPC appl... -
Singapore Semiconductor Testing Equipment Market Projected to Reach $310 Million by 2033, Growing at 7.8% CAGR
ABNewswire Singapore Overview This article provides an overview of a market research report on the Singapore semiconductor testing equipment market, distributed by ABNewswire. The report forecasts the market to reach $310 million by 2033... -
IEEE ECTC 2026 Highlights Packaging Technologies Redefining AI and HPC Scalability Limits
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The 2026 IEEE Electronic Components and Technology Conference (ECTC) spotlighted packaging technologies redefining AI and HPC scalability limits. Intel Foundry's R&... -
Cadence and Samsung Foundry Deepen 2nm and 3D-IC Collaboration to Meet Surging AI Infrastructure Demand
Chiplet News USA Overview Cadence and Samsung Foundry are deepening their collaboration in 2nm process technology and 3D-IC (3D Stacked Integrated Circuit) technology to address the surging demand for AI infrastructure and physical AI. T... -
Synopsys Enhances Power and Performance for AI and Multi-Die Designs on Latest Samsung Foundry Processes
Chiplet News USA Overview Synopsys announced solutions at SAFE Forum 2026 to enhance power efficiency and performance for AI and multi-die designs, leveraging Samsung Foundry’s latest process technologies. This initiative directly addres... -
Samsung Reportedly to Launch Physical AI Chiplet Platform Next Year, Accelerating AI Inference and Infrastructure
Design And Reuse South Korea Overview Samsung is reportedly planning to launch a physical AI chiplet platform as early as next year, aiming to accelerate next-generation chip development for AI inference and infrastructure. This platform... -
Fraunhofer IPMS Develops High-Density Chiplet Systems at Wafer Level, Advancing Integration for AI and HPC
Design And Reuse Germany Overview Fraunhofer IPMS has developed high-density chiplet systems at the wafer level, aiming to enhance integration for AI and high-performance computing (HPC) applications. This research contributes to the min...
