Bonding– tag –
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Semiconductor Back-End
Sub-10nm Residual Distortion Achieved in Low-Distortion Fusion Bonding with Pneumatically Curved Wafers for Advanced Semiconductors
arXiv USA Overview A recent arXiv publication reports the development of a novel low-distortion fusion bonding technique that employs pneumatically curved wafers to achieve an exceptionally low residual grid distortion of less than 10 na... -
Semiconductor Back-End
Samsung to Establish Gwangju Advanced Packaging Facility, Eyes Full HBM Hybrid Bonding Transition by 2029
TrendForce South Korea Overview Samsung Electronics is reportedly considering a new advanced semiconductor packaging plant in Gwangju, South Korea, with investment plans potentially announced by June 2026. This strategic facility will fo... -
Semiconductor Back-End
SK Hynix Boosts HBM4 Production with Major TC Bonder Order from Hanmi Semiconductor
The Korea Herald South Korea Overview SK Hynix has made a significant investment, ordering ₩44.2 billion (approx. $28.7 million USD) worth of advanced 'TC Bonder 4.5 Griffin' thermo-compression bonders from Hanmi Semiconductor. This stra... -
Semiconductor Back-End
IEEE ECTC 2026 Program Reveals Latest Research in Advanced Packaging, Including 3D Integration, Hybrid Bonding, and New Substrate Materials
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The program for the 76th IEEE Electronic Components and Technology Conference (ECTC) unveiled a wide array of cutting-edge research in advanced packaging, focusing ... -
Semiconductor Back-End
Hybrid Bonding Unlocks New Frontiers in 3D Integration, Driving AI Accelerators and Chiplet Designs
PatSnap UK Overview Hybrid bonding, an innovative 3D integration technology, enables both electrical continuity and mechanical integrity without solder or microbumps by combining metal-to-metal (primarily Cu-Cu) and dielectric-to-dielect... -
Semiconductor Back-End
AMD Announces Over $10 Billion Taiwan Ecosystem Investment to Bolster AI Infrastructure and Advanced Packaging Manufacturing
Electronics Engineering Herald - EEHerald USA Overview AMD announced an investment exceeding $10 billion in Taiwan's ecosystem to expand its AI infrastructure and advanced packaging manufacturing capabilities. This significant capital in... -
Semiconductor Back-End
CEA-Leti Demonstrates 1µm Pitch Die-to-Wafer Hybrid Bonding, Addressing AI Hardware Bottlenecks
Chiplet Marketplace France Overview CEA-Leti announced a significant advancement at ECTC 2026, demonstrating functional test vehicles utilizing die-to-wafer (D2W) hybrid bonding down to 1µm pitch, poised to resolve critical AI hardware b... -
Semiconductor Back-End
Imec and EV Group Set New World Record for 3D Chip Stacking Precision with Sub-40nm Wafer Bond Overlay
PR Newswire ベルギー Overview Imec and EV Group have achieved a world-record post-bond overlay accuracy of less than 40 nanometers across a 300mm wafer for 200nm pitch hybrid bonding, a crucial advancement for next-generation 3D ICs. Dem... -
Semiconductor Back-End
ASMPT Establishes Advanced Packaging Technology Advisory Council to Accelerate AI-Era Innovation
ASMPT Singapore Overview ASMPT has established an Advanced Packaging Technology Advisory Council (TAC) to address the growing importance of advanced packaging for next-generation computing and AI components. The TAC will focus on a broad... -
Semiconductor Back-End
Huawei’s “Tao Law” Proposes 1.4nm-Equivalent Chip Density via Logic Folding and Ultra-Fine Hybrid Bonding
China as a System China Overview Huawei has introduced the "Tao Law," a novel semiconductor process development aiming for 1.4nm-equivalent chip density within five years through "Logic Folding." This method distributes logic gates acros...