TSMC– tag –
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Semiconductor Back-End
NVIDIA’s AI Chip Supply Bottleneck Stems from TSMC’s Booked CoWoS Capacity, Intel EMIB Emerges as Alternative
BingX International Overview TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity is fully booked through 2026, with 52-78 week lead times, posing a severe supply bottleneck for NVIDIA. While NVIDIA reportedly secures 60... -
Semiconductor Back-End
NVIDIA’s 2027 CoWoS Supply Forecast Raised 69% to 1.1 Million Interposers; AMD to See Over 50% Growth: KeyBanc Asia Supply Chain Checks Reveal Strong Demand
TipRanks USA Overview KeyBanc analyst John Vinh's Asia supply chain checks reveal strong, persistent demand across the semiconductor ecosystem. NVIDIA's 2027 CoWoS supply forecast for Rubin and Rubin Ultra was raised 69% to 1.1 million i... -
Semiconductor Back-End
TSMC and NVIDIA’s ‘Glass Killer’: How Glass Core Substrates Will Revolutionize AI Chips by 2028
SETN Taiwan Overview Renowned analyst Kuo Ming-Chi reveals TSMC's secretive development of 'glass core substrates' in collaboration with NVIDIA, poised to be a game-changer for next-generation AI chip manufacturing. This innovative techn... -
Semiconductor Back-End
TSMC Achieves Record Q2 Revenue of $40.2B with 67.7% Gross Margin, CoWoS Fully Booked Through 2026, and Maps 14-Reticle Packaging
LongYield - Substack International Overview TSMC reported record Q2 2026 consolidated revenue of $40.20 billion and a gross margin of 67.7%, driven by robust AI chip demand and leading-edge nodes (7nm and below accounting for 77% of wafe... -
Semiconductor Back-End
TSMC’s N3 Node and Expanding CoWoS Capacity Solidify Nvidia’s Future, While HBM4 Multi-Vendor Qualification Reduces Supply Risk
Seeking Alpha USA Overview TSMC and ASML's raised guidance confirms persistent AI infrastructure demand-supply imbalance. TSMC's N3 node, utilized for Nvidia's Rubin GPUs, is fully booked, and CoWoS advanced packaging capacity is expandi... -
Semiconductor Back-End
TSMC Leads in Data Center Co-Packaged Optics, While Samsung Pursues Future AI Packaging with HBM, Logic, and SiPh Integration in ‘2.xD’ Technology
KuCoin International Overview TSMC leads the data center co-packaged optics (CPO) switch market, with Broadcom and NVIDIA already sampling or shipping CPO switches based on TSMC's technology. Concurrently, Samsung is developing '2.xD' ad... -
Semiconductor Back-End
TSMC’s CoWoS Supply to Reach At Least 200K Wafers Monthly by 2027, Accelerating Expansion to Meet Soaring AI Demand
DigiTimes Taiwan Overview TSMC is accelerating its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity expansion to meet robust AI chip demand, with market indications suggesting monthly output will reach at least 200,000 wafe... -
Semiconductor Back-End
TSMC Plans Three Advanced Packaging Plants at Chiayi Science Park, Targeting Mass Production by 2027 for AI and Quantum Tech
Taiwan News Taiwan Overview TSMC plans three advanced packaging plants at Taiwan's Chiayi Science Park, with two slated for mass production by 2027. These facilities will focus on AI, heterogeneous integration, and quantum technology, le... -
Semiconductor Back-End
Morgan Stanley Forecasts 93% CoWoS Demand Surge by 2027, Driven by AMD’s Venice CPU Shipments
KuCoin International Overview Morgan Stanley forecasts global CoWoS (Chip-on-Wafer-on-Substrate) demand to nearly double to 2.694 million wafers in 2027, a 93% increase from 1.394 million in 2026. This growth is predominantly driven by A... -
Semiconductor Back-End
Samsung Develops ‘2.xD’ Advanced Packaging Integrating HBM, Logic, and SiPh to Tackle AI Data Center Power and Data Bottlenecks
DigiTimes Taiwan Overview Samsung Electronics is developing '2.xD' advanced packaging technology that integrates HBM, logic chips, and silicon photonics (SiPh) into a single package. This innovation aims to resolve critical power consump...