New Technology– category –
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IEEE ECTC 2026 Program Reveals Latest Research in Advanced Packaging, Including 3D Integration, Hybrid Bonding, and New Substrate Materials
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The program for the 76th IEEE Electronic Components and Technology Conference (ECTC) unveiled a wide array of cutting-edge research in advanced packaging, focusing ... -
Tsinghua University Develops 3D Chip Design Tool Tailored for Huawei’s ‘LogicFolding’ Architecture
Tom's Hardware China Overview Tsinghua University in China has developed a 3D chip design tool specifically tailored for Huawei’s 'LogicFolding' architecture. This tool aims to optimize chip performance and efficiency for AI and HPC appl... -
IEEE ECTC 2026 Highlights Packaging Technologies Redefining AI and HPC Scalability Limits
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The 2026 IEEE Electronic Components and Technology Conference (ECTC) spotlighted packaging technologies redefining AI and HPC scalability limits. Intel Foundry's R&... -
Cadence and Samsung Foundry Deepen 2nm and 3D-IC Collaboration to Meet Surging AI Infrastructure Demand
Chiplet News USA Overview Cadence and Samsung Foundry are deepening their collaboration in 2nm process technology and 3D-IC (3D Stacked Integrated Circuit) technology to address the surging demand for AI infrastructure and physical AI. T... -
Synopsys Enhances Power and Performance for AI and Multi-Die Designs on Latest Samsung Foundry Processes
Chiplet News USA Overview Synopsys announced solutions at SAFE Forum 2026 to enhance power efficiency and performance for AI and multi-die designs, leveraging Samsung Foundry’s latest process technologies. This initiative directly addres... -
Samsung Reportedly to Launch Physical AI Chiplet Platform Next Year, Accelerating AI Inference and Infrastructure
Design And Reuse South Korea Overview Samsung is reportedly planning to launch a physical AI chiplet platform as early as next year, aiming to accelerate next-generation chip development for AI inference and infrastructure. This platform... -
Fraunhofer IPMS Develops High-Density Chiplet Systems at Wafer Level, Advancing Integration for AI and HPC
Design And Reuse Germany Overview Fraunhofer IPMS has developed high-density chiplet systems at the wafer level, aiming to enhance integration for AI and high-performance computing (HPC) applications. This research contributes to the min... -
SK Group Chairman Deepens AI Alliances with Nvidia and TSMC, Expanding Next-Gen HBM and Advanced Packaging Collaboration
The Korea Herald South Korea Overview SK Group Chairman Chey Tae-won has strengthened alliances with leading AI chipmakers, meeting with Nvidia CEO Jensen Huang and later with TSMC Chairman C.C. Wei in Taiwan. Discussions focused on expa... -
Marvell Unveils Industry’s First 102.4 Tbps AI Switch, Doubling Bandwidth for AI Data Center Networks
Advanced Packaging News USA Overview Marvell announced the industry's first 102.4 Tbps AI switch, setting a new benchmark for network bandwidth in AI data centers. This innovative switch doubles bandwidth compared to current top-performi... -
Hybrid Bonding Unlocks New Frontiers in 3D Integration, Driving AI Accelerators and Chiplet Designs
PatSnap UK Overview Hybrid bonding, an innovative 3D integration technology, enables both electrical continuity and mechanical integrity without solder or microbumps by combining metal-to-metal (primarily Cu-Cu) and dielectric-to-dielect...
