Semiconductor Back-End– category –
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AMD Explores Powertech’s FOPLP for Next-Generation Zen 7 CPUs, Eyeing Packaging Diversification
TechPowerUp USA Overview AMD is reportedly exploring Powertech Technology's Fan-Out Panel-Level Packaging (FOPLP) for its upcoming "Zen 7" CPUs, codenamed "Grimlock." This move signals AMD's strategic intent to build increasingly complex... -
Korea Addresses HBM Test Equipment Bottleneck by Fostering Domestic Suppliers
eferix.substack.com South Korea Overview South Korea has identified the HBM test equipment bottleneck, historically dominated by foreign companies like Advantest and Teradyne, as a national supply chain vulnerability. In response, SK Hyn... -
Huawei’s “Tao Law” Proposes 1.4nm-Equivalent Chip Density via Logic Folding and Ultra-Fine Hybrid Bonding
China as a System China Overview Huawei has introduced the "Tao Law," a novel semiconductor process development aiming for 1.4nm-equivalent chip density within five years through "Logic Folding." This method distributes logic gates acros... -
Heterogeneous Integration Advances with Hybrid Bonding, Tackling Critical Power and Thermal Challenges for AI and 5G/6G
IndexBox Global Overview Heterogeneous integration, particularly vertical chip stacking with fine-pitch interconnects, is crucial for future AI and 5G/6G electronics, dramatically reducing data travel distances and power consumption. Hyb... -
Tokyo Electron and Samsung Boost Capex for Hybrid Bonding Equipment Amid Advanced Packaging Shift
Mordor Intelligence Japan, South Korea Overview Tokyo Electron and Samsung are significantly increasing capital expenditures for hybrid bonding and general bonding equipment, targeting long-term growth in the Through-Silicon Via (TSV) ma... -
NVIDIA CEO Jensen Huang Projects $150 Billion Annual Investment in Taiwan’s AI Supply Chain
BigGo Finance Taiwan Overview NVIDIA CEO Jensen Huang announced that the company's annual procurement and investment in Taiwan's AI supply chain is projected to reach $150 billion in the future, a tenfold increase from $10-$15 billion fo... -
NVIDIA’s CoWoS Bottleneck Eases, HBM Supply Emerges as Primary Constraint for AI Accelerators
24/7 Wall St. USA Overview TSMC's CoWoS advanced packaging capacity for AI accelerators is expanding, projected to reach 35,000 wafers/month by late 2026 and up to 140,000 wafers/month by 2027, alleviating a long-standing bottleneck. How... -
Hanmi Semiconductor Forecasts HBM4 TC Bonder Rebound in Q2, Announces US Expansion Plans
BigGo Finance South Korea Overview Hanmi Semiconductor anticipates a significant rebound in HBM4 TC bonder orders from Q2 2026, driven by accelerating AI semiconductor demand, despite a Q1 slump during the HBM3E-to-HBM4 transition. The c... -
Pushing the Limits of 3D Integration: Imec and EVG Achieve Record 200nm Hybrid Bonding Pitch
imec ベルギー Overview Imec and EV Group (EVG) have announced a major breakthrough in 3D integration, demonstrating wafer-to-wafer hybrid bonding with an unprecedented 200nm copper interconnect pad pitch on 300mm wafers. Achieved with a ... -
ASE Unveils Industry-First Automated 310mm Panel-Level Packaging Line for AI and Chiplet Integration
AnySilicon Taiwan Overview Advanced Semiconductor Engineering (ASE) has developed an automated 310mm x 310mm panel-level packaging (PLP) production line, a significant advancement for AI processors and chiplet architectures. This industr...
