Taiyo Holdings and imec Unveil 700nm 3-Layer RDL Breakthrough for Next-Gen AI Packaging

September 13, 2026

Quantum Zeitgeist Japan, Belgium

Overview

Taiyo Holdings, in collaboration with imec, announced at IEEE ESTC 2026 the successful formation of a 3-layer Redistribution Layer (RDL) with a critical dimension of 700 nanometers on 12-inch wafers. This achievement, enabled by their new FPIM series materials, marks a significant advance in fine-pitch wiring, crucial for high-density interconnections in advanced semiconductor packaging for AI and high-performance computing (HPC) chips. The materials demonstrate high compatibility with essential dual damascene processes for sub-1.6 micrometer pitches.

In Depth

The Packaging Imperative for AI

As the demand for artificial intelligence (AI) and high-performance computing (HPC) continues its exponential growth, the semiconductor industry is increasingly looking beyond traditional transistor scaling (Moore’s Law) for performance gains. Advanced packaging, particularly chiplet integration and high-density interconnections, has emerged as a critical enabler. Redistribution Layers (RDLs) serve as the vital ‘bridges’ that efficiently and rapidly connect multiple chiplets within a package. However, as packages grow larger and the number of wiring layers increases, the limitations of existing substrate materials and fine processing technologies have become significant bottlenecks, constraining the evolution of next-generation AI accelerators and High Bandwidth Memory (HBM).

A Precision Leap in Advanced Packaging

At the IEEE ESTC 2026 conference, Taiyo Holdings announced a groundbreaking collaboration with imec, successfully demonstrating the formation of a 3-layer Redistribution Layer (RDL) with an unprecedented critical dimension (CD) of 700 nanometers on 12-inch wafers. This achievement represents a crucial step forward in fine-pitch wiring for advanced semiconductor packaging. Enabled by Taiyo Holdings’ newly developed FPIM series materials, this technology is poised to dramatically increase connection density between chips, establishing a foundational technology for the continued evolution of high-performance AI chips and HPC packaging.

Enabling Ultra-Fine-Pitch Wiring: The Role of FPIM and Dual Damascene

RDLs are multi-layered wiring structures designed to provide electrical connections between chiplets or between chips and external packages. Their miniaturization is paramount for enhancing overall packaging density and performance. Taiyo Holdings’ new FPIM series materials played a pivotal role in this breakthrough, exhibiting superior processability, electrical properties, and reliability essential for achieving 700nm precision in 3-layer RDL formation. A key insight from imec’s analysis confirms that a dual damascene process is indispensable for realizing wiring pitches below 1.6 micrometers. Crucially, Taiyo Holdings’ new FPIM materials demonstrate high compatibility with this dual damascene process, positioning them as a key enabler for next-generation ultra-fine-pitch wiring technologies. This innovation is also expected to contribute to improved yield and reduced manufacturing costs in wafer-level thin-film processing.

Shaping the Future of AI and HPC

The successful development of 700nm high-precision RDL formation technology pushes the boundaries of current advanced packaging capabilities. This innovation is likely to play a significant role in future standardized packaging platforms by enabling the integration of more functions and higher performance into limited space, particularly in high-density interposers and advanced chiplet integration schemes. The collaborative research between Taiyo Holdings and imec underscores the critical importance of material and process innovations in the semiconductor backend for advancing computational power in the AI era. It is anticipated that the application of the FPIM series materials and this advanced RDL technology in mass production will substantially enhance the design flexibility and manufacturing efficiency of high-performance chips, paving the way for even more powerful and compact computing solutions.

Source: https://quantumzeitgeist.com/three-layer-rdl-taiyo-holdings-700/

Get our weekly technology intelligence — free

Receive an infographic that lets you judge at a glance whether each field’s analysis report is worth reading.

Subscribe Free — Weekly Tech Intelligence

By subscribing, you’ll receive Troy-Technical’s weekly technology intelligence newsletter.