TSMC to Boost 2nm and 3nm Advanced Process Capacity by up to 22% by Mid-2027 to Meet Soaring AI/HPC Demand

September 20, 2026

BigGo Finance Taiwan

Overview

TSMC plans a significant capacity expansion for its 2nm and 3nm advanced processes to meet surging demand for AI and HPC chips. The 2nm monthly capacity is projected to increase by approximately 22% to 110,000 wafers by mid-2027 from 90,000 wafers at the end of 2026, while 3nm capacity will rise by over 16% to 210,000 wafers from 180,000. This expansion, coupled with a planned doubling of CoWoS advanced packaging capacity by 2028, aims to bolster the comprehensive supply for AI chips.

In Depth

Key Findings

TSMC, a pivotal player in the global semiconductor industry, is set to significantly ramp up its production capacity for leading-edge 2nm and 3nm process technologies by mid-2027. This aggressive expansion, with increases of up to 22% for 2nm and over 16% for 3nm, directly addresses the escalating global demand for AI and High-Performance Computing (HPC) chips, which are central to the next wave of technological innovation.

Technical / Clinical Details

Specifically, TSMC’s monthly production capacity for 2nm process technology is projected to grow from 90,000 wafers at the end of 2026 to approximately 110,000 wafers by mid-2027, representing a 22% increase. Concurrently, 3nm process capacity will expand from 180,000 wafers to 210,000 wafers, an increase of over 16%. These advanced nodes are critical for manufacturing the most powerful and energy-efficient AI accelerators, CPUs, and GPUs. This fabrication capacity boost is synergistically aligned with TSMC’s plans to double its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity to 260,000 wafers per month by the end of 2028, effectively tackling critical bottlenecks in advanced chip integration. Meanwhile, Intel’s EMIB-T (Embedded Multi-die Interconnect Bridge – Tiled) packaging technology is also gaining traction, reportedly well-suited for custom AI accelerators from major clients like Google and Amazon, with MediaTek also expressing positive feedback on EMIB. Intel aims for 40,000-45,000 wafer-equivalent EMIB-T capacity by 2028.

Background & Context

The burgeoning complexity of AI models and the exponential growth of data require ever more sophisticated and power-efficient processing units. This surge has placed immense pressure on the supply chain for leading-edge silicon fabrication and advanced packaging. As the preeminent foundry, TSMC’s strategic investments are crucial for meeting this demand and supporting the product roadmaps of tech giants like NVIDIA, Apple, and Qualcomm. The current landscape highlights HBM (High Bandwidth Memory) and CoWoS packaging as key constraints in the AI chip supply chain, making TSMC’s holistic approach to expanding both front-end (wafer fabrication) and back-end (packaging) capacities strategically vital for stabilizing the ecosystem.

Strategic Significance & Outlook

TSMC’s simultaneous expansion of both advanced process nodes and CoWoS packaging capacity is poised to have a profound impact across the entire AI chip ecosystem. By stabilizing and increasing supply, more companies will be enabled to develop and deploy groundbreaking AI products, broadening the application of AI technologies across various industries. The competitive landscape, further shaped by Intel’s EMIB-T advancements and the contributions of OSAT providers, indicates an unprecedented era of investment and innovation in semiconductors. This intensified competition is set to define the future of computing, pushing the boundaries of what AI can achieve.

Source: https://finance.biggo.com/news/b8e1ef85-db81-4a2a-a33b-b419fe0c005f

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