Chiplet– tag –
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New Technology
AZoM Explains Polyimides’ Indispensable Role in Semiconductor Packaging, Critical for HBM and Chiplet RDLs
AZoM UK Overview AZoM has detailed the indispensable, multifunctional role of polyimides in semiconductor packaging, simultaneously providing insulation, adhesion, pattern definition, and stress control at the thin-film interface between... -
Semiconductor Back-End
Laser Debonding Technology Becomes Critical for Improving Thin Wafer Yield in HBM and Hybrid Bonding
Microtreat Global Overview Laser debonding is gaining importance as the cleanest and least damaging wafer separation technology for high-value 3D integration and advanced packaging. For ultra-thin wafers (20-50 micrometers) in HBM, chipl... -
Semiconductor Back-End
Taiyo Holdings and imec Unveil 700nm 3-Layer RDL Breakthrough for Next-Gen AI Packaging
Quantum Zeitgeist Japan, Belgium Overview Taiyo Holdings, in collaboration with imec, announced at IEEE ESTC 2026 the successful formation of a 3-layer Redistribution Layer (RDL) with a critical dimension of 700 nanometers on 12-inch waf... -
Semiconductor Back-End
Hybrid Bonding Equipment Market Projected to Reach $1.73 Billion in 2026, Growing to $2.58 Billion by 2032
360iResearch Global Overview This article provides an overview of a market research report published by 360iResearch. The hybrid bonding equipment market is projected to reach $1.73 billion in 2026, with a compound annual growth rate (CA... -
Semiconductor Back-End
Taiwan’s MOEA Unveils 29 Cutting-Edge Semiconductor Innovations, Including Double-Sided RDL Process for CoPoS Packaging at SEMICON Taiwan 2026
Ministry of Economic Affairs (MOEA) Taiwan Overview Taiwan's Ministry of Economic Affairs (MOEA) showcased 29 cutting-edge technology innovations at SEMICON Taiwan 2026, encompassing advanced packaging, AI data center power management, a... -
Photonics
MIT/NY CREATES Develops 300mm Process for Flexible, Transparent Silicon Photonics; Counterpoint Predicts NPO to Outpace CPO in Adoption
Semiconductor Engineering USA Overview Researchers at MIT and NY CREATES have developed a 300mm manufacturing process for flexible, transparent silicon photonics using standard semiconductor techniques. While optical chiplets offer a pro... -
Photonics
MITRE Corporation Funds Development of All-Optical Chiplets Targeting 2-3 Orders of Magnitude AI Energy Efficiency Boost
The MITRE Corporation USA Overview Funding from The MITRE Corporation is supporting small-scale R&D into all-optical computer chiplets based on photonic integrated circuits for optical computing. Successful implementation of this pro... -
New Technology
TSMC’s CoWoS Drives AI Semiconductor Demand, Japanese Material Suppliers Expand Ecosystem in Taiwan
The Economy Taiwan Overview TSMC's CoWoS advanced packaging technology is a primary driver for demand in AI accelerators and HBM, leading Japanese material suppliers like Namics (underfill) and Fujifilm (CMP slurry) to expand operations ... -
Semiconductor Back-End
TRUMPF Resolves Glass Substrate TGV Coating Bottleneck with High-Power HiPIMS, Accelerating Next-Gen AI Chip Packaging
TRUMPF Germany Overview TRUMPF has introduced a High-Power Impulse Magnetron Sputtering (HiPIMS) approach to address a key manufacturing challenge in next-generation AI chip packaging: reliably coating millions of minute Through-Glass Vi... -
Semiconductor Back-End
Glass Substrates Emerge as Key Breakthrough for Next-Gen AI Chip Packaging: Intel, TSMC, Samsung Accelerate Development
Industry Analyst International Overview Glass substrates are increasingly recognized as a critical breakthrough for next-generation AI chip packaging, with industry leaders like Intel, TSMC, and Samsung Electro-Mechanics accelerating the...