Chiplet– tag –
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Glass Substrates: The Next Frontier in AI Packaging and the Race to Mass Production
The Economy South Korea Overview Glass substrates are rapidly emerging as a transformative technology in advanced AI chip packaging, poised to replace conventional organic substrates and silicon interposers by offering superior dimension... -
Europe Boosts Investment in Advanced Packaging and Chiplet Integration; imec’s FAMES Pilot Line Aims to Mitigate Regional Supply Chain Risks
Astute Group UK Overview Europe is significantly increasing investment in advanced packaging and chiplet integration technologies to diversify its semiconductor supply chain and reduce regional procurement risks, shifting focus from pure... -
Silicon Box Secures $77.5M to Scale Advanced Packaging and Chiplet Integration
DealStreetAsia Singapore Overview Singapore-based semiconductor packaging and chiplet integration startup, Silicon Box, has secured S$100 million (approximately US$77.5 million) in debt financing from a global consortium of institutional... -
SemiMedia Reports China Accelerating Global Catch-Up in Advanced Packaging Materials for AI and HPC
SemiMedia China Overview A SemiMedia report indicates that China is accelerating its global catch-up in advanced packaging materials, driven by the demand for AI chips and high-performance computing (HPC). The focus is on developing high... -
IEEE ECTC 2026 Program Reveals Latest Research in Advanced Packaging, Including 3D Integration, Hybrid Bonding, and New Substrate Materials
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The program for the 76th IEEE Electronic Components and Technology Conference (ECTC) unveiled a wide array of cutting-edge research in advanced packaging, focusing ... -
IEEE ECTC 2026 Highlights Packaging Technologies Redefining AI and HPC Scalability Limits
IEEE Electronic Components and Technology Conference (ECTC) USA Overview The 2026 IEEE Electronic Components and Technology Conference (ECTC) spotlighted packaging technologies redefining AI and HPC scalability limits. Intel Foundry's R&... -
Cadence and Samsung Foundry Deepen 2nm and 3D-IC Collaboration to Meet Surging AI Infrastructure Demand
Chiplet News USA Overview Cadence and Samsung Foundry are deepening their collaboration in 2nm process technology and 3D-IC (3D Stacked Integrated Circuit) technology to address the surging demand for AI infrastructure and physical AI. T... -
Synopsys Enhances Power and Performance for AI and Multi-Die Designs on Latest Samsung Foundry Processes
Chiplet News USA Overview Synopsys announced solutions at SAFE Forum 2026 to enhance power efficiency and performance for AI and multi-die designs, leveraging Samsung Foundry’s latest process technologies. This initiative directly addres... -
Samsung Reportedly to Launch Physical AI Chiplet Platform Next Year, Accelerating AI Inference and Infrastructure
Design And Reuse South Korea Overview Samsung is reportedly planning to launch a physical AI chiplet platform as early as next year, aiming to accelerate next-generation chip development for AI inference and infrastructure. This platform... -
Fraunhofer IPMS Develops High-Density Chiplet Systems at Wafer Level, Advancing Integration for AI and HPC
Design And Reuse Germany Overview Fraunhofer IPMS has developed high-density chiplet systems at the wafer level, aiming to enhance integration for AI and high-performance computing (HPC) applications. This research contributes to the min...
